|
Issue Highlights
Editor's Note
For
years, Moore's Law and the shrinking transistor boosted processor
speeds on a regular basis. Eventually, however, microlithography could
no longer come to the rescue, forcing developers to invent new
approaches like instruction-level parallelism, pipelining, and the
issuing of multiple instructions per cycle. When it comes to memory, we
find ourselves at that critical junction where simply throwing more
gates at the problem is not enough to allow read/write operations to
keep up with processor demand. The solution is a whole new approach,
says the author of this week's feature. Find out why we need a new metric for memory speed and what a
software-based solution called algorithmic memory can do to help us
break down the memory wall. 
What do elephants and nuclear waste have in common? Both need memory
that lasts a millenium. That's a hard trick in a
world where data storage formats turn over in a matter of years. Got
any ideas? The nuclear-storage guys do--and they've built and tested
it.
We also have plenty of news and products waiting for you, so be sure to
stop by the Memory Designline and take a look around. I welcome your
feedback and would love to hear from you about particular topics you
would like to see us cover. Have an idea for a contributed article?
Drop me a line and we can get the process started.
Until next week,
Kristin Lewotsky
Editor, Memory Designline
Klewotsky@chezhardy.com
How Tos
Memory
operations per second (MOPS) provides a better metric for assessing new
techniques like algorithmic memory.
Temporary
networks formed with compact, portable satellite base stations give
broad, robust access in emergencies.
Memory
test, repair, and diagnostic solutions can improve both the
manufacturing process and device performance.
TI's
Priya Thanigai provides some real world examples of where ferroelectric
random access memory should be considered as an alternative to flash as
a viable nonvolatile memory technology.
Although
multi-level cell NAND flash offers a cost advantage, single-level cell
NAND flash delivers longer lifetime, lower error rates, and better
performance for mission-critical applications.
FPGAs
connected to gigabytes of DDR is now common, so attention must be paid
to the probability and avoidance of soft errors.
Non-volatile
memory technology addresses demands of SoCs controlling 24/7 connected
devices.
So
you think high-level synthesis is just for dataflow? Think again after
Forte shows you how it can help you with control-dominated design…
Although
IC manufacturers have been extremely successful in reducing defects, on
the other hand a significant part of the quality drive for
printed-circuit-board module makers is stemming from reducing
electrical over-stress (EOS), electrostatic discharge (ESD), and cases
of no-trouble-found (NTF). Solution of these problems requires the
involvement of the PCB module maker and the automotive manufacturer as
well.
A
look at the basics, the evolution of the technology, and design tips.
How
it works, the latest advances, and progress toward commercial
viability.
Learn
about various timing parameters and their impact on the performance of
the DRAM.
Products
The
XceedIOPS2 leverages 24-nm eMLC NAND flash for mainstream workloads.
Design
uses low cost, low power MachXO2 PLD
Designed
for enterprise server systems, the units use 40% less power than DDR3
versions.
Lattice
Diamond 2.0 includes advanced data support for timing, power, and
packaging for new low-cost, low-power LatticeECP4 FPGA family.
The
ICs offer up to 64-bit resolution, direct pin-access, and fast
frequency tuning for for frequency-agile wireless applications.
Three
new NVM product families serve system-on-chip and fabless firms.
Based
on Altera Stratix V GX FPGA, new half-height board delivers PCIe 3.0
x8, 40G Ethernet and DDR3 SDRAM interfaces, enabling quick
time-to-market
The
AT24MAC series provides pre-programmed MAC/EUI node identity addresses,
while the AT24CS devices include factory-programmed, read-only serial
numbers for easier inventory control.
News
Japan's
Toshiba it cut its production of flash memory chips by about 30 percent
due to market oversupply and price declines.
Micron
move to acquire Elpida Memory is a bold one that carries risk,
particularly if the integration and technology transfer does not go
smoothly, according to market research firm IHS iSuppli.
Data
traffic is expected to grow ten-fold from 2010 to 2015 and up to
100-fold by 2020, according to a new report from the IEEE's Ethernet
standards group.
Claiming
to offer the first phase change memory in high-volume production, U.S.
memory chip vendor Micron Technology announced availability of its
45-nm PCM for mobile devices.
Chip
vendor Integrated Silicon Solution signed a deal to acquire specialty
memory chip vendor Chingis Technology for $33 million in cash.
Ferroelectric
random access memory supplier Ramtron has entered into a new
manufacturing and license partnering agreement with Rohm Co., Ltd. to
manufacture Fram-based semiconductor products for Ramtron on Rohm's
Fram manufacturing line.
DRAM
pricing is set to increase as inventory levels fall relative to demand,
according to a new report from market research firm IHS iSuppli.
Shipments
of tablet computers will surpass those of notebook computers in 2016,
according to market analysis firm NPD DisplaySearch.
|
