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Accelerate Your Design Leveraging Altera’s Partners
This
month’s update highlights new development kits and IP, along with
hands-on demos from Altera Solution Acceleration Partners (ASAP). See
how these proven, ready-to-integrate solutions can accelerate your next
build—from edge AI to mission-critical applications.
Accelerate Macro‑Cell Radio Design with a Proven Altera and Hitek Systems Enablement Package
Designing next‑generation macro and microcell radios requires balancing performance, scalability, and standards compliance - without increasing system integration risk. Altera, Texas Instruments, and Hitek Systems have jointly validated a macro cell enablement package that gives RAN architects a proven foundation for OpenRAN‑ready radio platforms.
The collaboration delivers a hardware‑validated reference architecture integrating Altera Agilex® 7 FPGAs, TI’s AFE7769D quad‑channel RF transceiver, and Hitek’s production eSOM FPGA platforms.
The live demo validates critical radio datapaths and control
interfaces, confirming that key RF‑digital integration points operate
correctly and predictably from initial bring‑up.
Why it matters
For
RAN architects, one of the highest risks in radio design is aligning RF
processing, digital front‑end functions, and baseband scalability while
meeting evolving OpenRAN and 3GPP requirements. This reference platform
reduces that risk with a validated JESD204C single‑link interface, pre‑integrated software, and a modular architecture that scales from 4T4R to 8T8R configurations and beyond without redesigning core subsystems.
By offloading crest factor reduction (CFR) and digital predistortion (DPD)
to the RF front end, the platform simplifies system partitioning and
frees FPGA resources for higher‑value scheduling and control‑plane
functions. Combined with Hitek’s proven FPGA design services, the
solution seamlessly brings together Altera and TI technologies.
What you gain
- A proven radio subsystem architecture aligned with OpenRAN deployment needs
- Reduced integration risk through validated RF‑to‑FPGA interoperability
- Improved power efficiency and system simplicity using hardware‑accelerated CFR and DPD
- A scalable path across the Altera Agilex portfolio and Hitek eSOM platforms
Read the full blog to
see the validated demo and learn how this architecture accelerates
OpenRAN macro and microcell radio development with greater confidence.
Build Secure, Future-Ready Networks That Adapt as Fast as Your Requirements
As embedded and edge systems evolve,
fixed‑function networking struggles to keep up with changing protocols,
latency requirements, and rising security expectations. Altera and Pantherun have partnered to deliver a P4‑based, FPGA‑accelerated networking platform designed for configurable, secure, and high‑performance data planes that can adapt over time.
The solution combines Altera FPGA platforms and P4‑programmable packet processing pipelines with Pantherun’s Lithe network IP engine
- a modular, runtime‑configurable Layer 2/3 networking stack
implemented entirely in programmable logic. Together, they offer an
alternative to rigid ASIC‑based designs, delivering ASIC‑class throughput with FPGA‑level flexibility for industrial, telecom, and mission‑critical systems.
Why this matters
Networking
requirements rarely remain static over the lifetime of a product.
Protocols evolve, security expectations tighten, and performance demands
increase — often long after hardware is deployed. This architecture
allows developers to modify network behavior over time using P4‑based
workflows, while maintaining deterministic, ultra‑low‑latency
performance across 1G to 100G platforms. Security is embedded directly into the data path using FPGA‑resident, inline encryption based on Pantherun’s Stealth AES IP, eliminating software bottlenecks and reducing attack surface without adding latency.
What you gain
- Programmable control: Adapt L2/L3 packet processing as protocols change — without hardware redesigns
- High performance with flexibility: Ultra‑low‑latency switching and routing with ASIC‑class throughput
- Security by design: Inline, FPGA‑based encryption integrated directly into the data plane
- Longer system lifecycles: Reconfigurable hardware that evolves with standards and security requirements
Read the full blog to see how Altera and Pantherun enable flexible, secure, and future‑ready networking architectures for next‑generation systems.
Keep Your Aurora Links—and Expand Your Design Freedom with Altera FPGAs
If your system relies on Aurora 64B/66B or Aurora 8B/10B for high‑speed, low‑latency data movement, you shouldn’t need a redesign to adopt new FPGA platforms. The Aurora 64B/66B IP Core and Aurora 8B/10B IP Core from ALSE let you reuse proven Aurora‑based architectures while deploying on Altera FPGAs, including Agilex 5 and Agilex 7.
Why you should care
Teams
are under pressure to reuse proven architectures, broaden FPGA options,
or migrate designs—without disrupting validated data paths. ALSE
removes this friction with full protocol compatibility and seamless interoperability on Altera FPGAs, preserving your architecture while expanding flexibility.
What’s in it for you
- Protect your investment – Retain your existing Aurora 64B/66B data path and avoid costly redesigns while targeting Altera’s newer Agilex FPGAs.
- Lower migration risk – Use a hardware‑verified IP core proven across multiple Altera platforms and adopted by global customers.
- Accelerate time to market – Leverage reference designs, application notes, and user guides to streamline design‑in and validation.
Proven on modern Altera platforms
ALSE delivers a working Agilex 5 hardware demo (See Video), that validates Aurora 64B/66B interoperability in real silicon, giving your team confidence before you commit.
Explore the ALSE Aurora 64B/66B IP Core and Aurora 8B/10B IP Core to preserve your high‑speed links while expanding to Altera FPGA platforms.
Cut Network Latency and CPU Load with Hardware-Accelerated QUIC on Altera FPGAs
QUIC is a next‑generation, fully encrypted transport protocol that integrates connectivity and security - replacing the traditional TCP + TLS stack to deliver lower latency, improved reliability, and seamless mobility. It is the transport foundation for HTTP/3.
As adoption of QUIC and HTTP/3 accelerates across cloud, networking,
and edge applications, performance expectations are rising along with
traffic volumes.
As
applications move to encrypted, low‑latency connectivity,
software‑based networking stacks struggle to keep up. While QUIC and
TLS 1.3 improve security and responsiveness, implementing them entirely
in software can overload CPUs, increasing latency and limiting
throughput in edge, networking, and datacenter designs.
The QUIC Client 1Gbps IP Core and QUIC Server 10Gbps IP Core from Design Gateway
move QUIC and
TLS 1.3 entirely into FPGA hardware. By offloading encrypted transport,
congestion control, and cryptography onto Altera FPGAs, designers
achieve faster connections, lower latency, and near wire‑speed
performance - without consuming valuable CPU resources.
Why it matters
Systems
handling large numbers of encrypted connections require predictable
latency and efficient CPU utilization. Hardware‑accelerated QUIC enables
0‑RTT session resumption and native multi‑streaming without head‑of‑line blocking, delivering faster response times as traffic scales.
What you gain
- Lower‑latency networking with hardware‑based QUIC features such as 0‑RTT connection setup and parallel streams
- Reduced CPU load by offloading QUIC, UDP/IP, and TLS 1.3 processing into FPGA hardware
- Secure, scalable throughput with 1G/10G QUIC engines conforming to RFC 9000 and TLS 1.3
Watch the QUIC1GC IP demo on Agilex 5 FPGA, showcasing hardware‑accelerated QUIC and HTTP/3 with real‑time CPU offload.
Stop DDoS Attacks at Line Rate with Altera FPGA‑Accelerated SmartNIC Protection
At
100G, 400G, and beyond, modern DDoS attacks overwhelm CPU‑based
defenses before mitigation can even begin. The result: degraded
performance, lost availability, and increased infrastructure cost.
The DYNANIC Anti‑DDoS solution, running on DYNANIC-powered Silicom ThunderFjord SmartNICs, stops attacks inline at wire speed.
Traffic is filtered directly in SmartNIC hardware, blocking malicious
packets before they reach the host—while legitimate traffic continues
flowing with ultra‑low latency, even during
massive attacks.
Why it matters
CPU‑
and software‑based DDoS protection can’t absorb today’s packet rates,
and fixed ASIC solutions can’t adapt fast enough. DYNANIC moves
mitigation into the data path, eliminating CPU bottlenecks and enabling real‑time, adaptive protection without external scrubbing infrastructure.
What you gain
- Line‑rate mitigation – Stop volumetric DDoS attacks inline at up to 400 Gbps, with no impact to clean traffic
- CPU freedom – Offload packet filtering from the host, freeing cores for revenue‑generating workloads
- Ultra‑low latency – Trusted traffic bypasses the CPU entirely, even under attack
- Future‑proof security – Adapt to new attack patterns through FPGA updates—no hardware replacement required
- Fast deployment – Full control through standard software APIs, with no FPGA expertise needed
See it live: Watch DYNANIC stop a real‑time DDoS attack at full line rate on an Altera Agilex‑powered Silicom ThunderFjord SmartNIC—before system performance is impacted.
Deterministic, Ultra-low latency FinTech Acceleration: See BittWare and Napatech at STAC New York
As
trading and analytics systems push toward tighter latency and higher
predictability, deterministic infrastructure is becoming essential. At STAC Summit – New York (May 20), BittWare and Napatech
will showcase Altera FPGA-based solutions designed for ultra-low
latency, precise timing, and consistent performance in modern financial
markets.
BittWare will demonstrate its Agilex 7 I-Series FPGA boards with a fully hardware-accelerated network stack and White Rabbit precision timing, enabling deterministic sub‑microsecond packet processing, accurate timestamping, and reduced CPU load - ideal for latency‑sensitive trading environments.
Napatech will highlight its Agilex 7 FPGA‑powered SmartNICs, DPUs, and XPUs, supporting everything from high‑fidelity market simulation to real‑time AI inference. With line‑rate packet processing and microsecond‑level inference, these platforms help firms deploy AI‑driven strategies without compromising determinism.
Visit STAC New York to see how FPGA-based acceleration from BittWare and Napatech can deliver measurable performance gains for modern FinTech workloads.
Accelerate FPGA Design Insight into Real‑World Systems: Altera and Partners at CERN FPGA Developers’ Forum
The CERN FPGA Developers’ Forum (May 27–29)
brings FPGA engineers together to share real‑world implementation
experience—from tool flows and architecture decisions to lessons learned
that rarely surface in traditional conferences. At the event, Altera and partners iWave, Knowledge Resources, and PRO DESIGN will demonstrate how Agilex™ FPGA‑based platforms help teams reduce design risk, simplify integration, and accelerate development.
Altera will showcase Agilex 9 SoC FPGA Direct RF-Series and Agilex 7 FPGAs and SoC FPGA platforms, highlighting scalable acceleration approaches used in demanding, real‑world system designs.
iWave will demonstrate its wide portfolio of Agilex‑based SoMs and COTS boards, including a live cockpit GUI demo on its Agilex 9‑based iG‑G67M Direct RF
SoM. These solutions enable rapid deployment of compact,
high‑performance systems while maintaining deterministic behavior and
design flexibility.
Knowledge Resources will highlight its Agilex 9‑powered KRM-10A9W027 SoM, combining wideband RF and massive FPGA compute
on a single module. By tightly integrating RF and processing, the
platform simplifies system architecture and shortens time to deployment
for advanced sensing and instrumentation applications.
PRO DESIGN will present its 400G‑ready FALCON Agilex 7M Acceleration Card,
designed for memory‑intensive, low‑latency workloads. The platform
delivers scalable, deterministic acceleration for next‑generation
compute and networking architectures.
Register for the CERN FPGA Developers’ Forum to see these platforms in action—and talk with Altera about accelerating your next FPGA design.
Inspect High‑Speed Networks Without Data Overload: See Napatech at ISS World Europe
As
encrypted traffic volumes explode, security teams are struggling to
inspect, filter, and act on high‑risk data — without overwhelming
servers or missing threats. At ISS World Europe in Prague (June 2–4), Napatech (Booth #118) will show how to remove unwanted data at n × 100 Gbps while maintaining full visibility and line‑rate
performance.
Powered by Agilex 7 FPGAs, Napatech’s Altera‑based SmartNICs and DPUs offload deep packet inspection directly into hardware. This approach enables security teams to filter video, encrypted traffic, and other non‑essential data at the network edge, reducing CPU load, lowering latency, and delivering faster, more deterministic threat
detection.
See it live in Napatech’s technical presentation, “Remove unwanted data (e.g., video, encrypted traffic, etc.) at n × 100 Gbps using an ultra‑compact server” on June 2, 16:10–17:00, and experience how hardware‑accelerated inspection scales with modern networks.
Visit Napatech at ISS World Europe to see how Altera FPGA‑based acceleration simplifies high‑speed security inspection.
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