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From Fluid Handling to Dose Control: How Valve Technology Evolved from Process Component to Dose-Control Enabler
By Jeff DeWitt, Lead Applications Engineer, Swagelok Company
As semiconductor requirements advance, valve performance becomes a system-level consideration.
Enabling Next-Generation Plasma Dicing with Ultrasonic Spray Coating and Digital Lithography
By Johanna Rimböck and Jakob Holzapfel, EV Group
A conformal, photo-sensitive coating combined with maskless lithography enables clean, low-stress plasma dicing over complex bump, pillar and cavity structures — without film frame, tape or added contamination risk.
Advanced Packaging Process Control Through Full-Field Wafer Shape Using WFPI
By Miguel Jimenez-Gomis, Senior Application Engineer, Wooptix
Wavefront phase imaging captures the full-wafer shape and stress signatures that traditional metrology misses, giving fabs a real-time handle on the bonding-induced distortions that threaten yield in backside power delivery and HBM stacks.
From Lab to Fab: The Rise of HiPIMS in Semiconductor Manufacturing
By Waldemar Schönberger, Wahyu Diyatmika, Markus Berendt and Frank Benecke, VON ARDENNE GmbH
High-power impulse magnetron sputtering delivers denser, better-adhering films than conventional sputtering — but scaling it past the lab bench takes more than turning up the power.
From Wafers to Panels: Overcoming Lithography Challenges in Advanced Packaging
By Stéphane Pellegrini, Product Manager, ETEL, and Shahbaz Sohrab, Business Development Specialist – Semiconductor, HEIDENHAIN
As advanced packaging shifts from wafer-level to panel-level formats, overlay accuracy, throughput, and thermal stability are redefining what lithography stages must deliver.
Diamonds to Save the Data Center
By Dhrumil Rangani, Co-Founder, Karia Technologies
Heat is now a first-order packaging constraint. Near-junction diamond is how the package fights back.
AMHS Is Not Just Factory Logistics
By Moh Kolbehdari, Ph.D., Senior Director of IC/Packaging, Socionext America
As semiconductor fabs become more automated, material movement increasingly carries process context, technical eligibility and manufacturing consequence.
Why Is AI Finally Sticking Inside the Fab?
By Mahima Sambre, Acumen Research and Consulting
Fabs are not buying a fab-wide AI platform. They are buying narrow, deterministic tools tied to whichever process step is bleeding the most yield.
The Measurement Gap: Why Metrology and Inspection Is Outgrowing the Industry’s Ability to Supply It
By Clara Grcevic, Market & Technology Analyst, Semiconductor Equipment, Yole Group
Metrology and inspection are the only family of process steps that add nothing to the wafer, yet the segment is under mounting pressure as the AI-driven memory and equipment cycle accelerates.
How to Tackle Hidden Production Risks in Semiconductor Operations
By Craig Walters, Vice President, Business Process Outsourcing, Semiconductor, Kelly
By applying a disciplined, engineering-rooted approach to risk identification, semiconductor manufacturers and their outsourcing partners can systematically reduce the quality and safety exposure hidden inside the most routine manual operations — before a costly incident forces the issue.
Why SiC and GaN Need Their Own Qualification Standards
By Pradyumna Gupta, Ph.D., Founder & Chief Scientist, Infinita Lab; Founder & CEO, Infinita Materials
SiC and GaN power devices are moving into EV inverters, on-board chargers, solar strings and data center power supplies faster than the qualification standards meant to vouch for them — and the gap between silicon-era testing and wide-bandgap failure physics is more than academic.
Optical Stability Is Becoming a Process-Control Issue
By Sabina Kuprėnaitė, Ph.D., Head of R&D, OPTOMAN
Surviving a laser pulse and staying optically stable across billions of them are different qualification questions — and as AI-driven fab investment pushes more advanced tools into production, the gap between the two is becoming a process-control problem in its own right.
Stacking Up: Inside the Industry’s Race to Build CFET Transistors
Intel, TSMC, Samsung, and IBM Research are converging on complementary FET architecture as the successor to gate-all-around — and recent papers at IEDM and the VLSI Symposium show the technology moving from concept to working silicon.
The Five Factors Defining the Next Generation of AI Inference Chips
By Ankur Saxena, Investment Director, TDK Ventures
As AI moves from training to deployment, inference chips will be judged less on raw TOPS than on five linked factors — performance, price, power, privacy and programmability — and the market is likely to reward a portfolio of specialized architectures rather than a single winner.
Why “Faster Chips” Don’t Feel Faster
By Faraj Aalaei, Founder and CEO, Cognichip
Raw processing speed no longer translates directly into systems that feel faster. The bottleneck is how thousands of components work together — and closing that gap means rethinking how decisions get made early in chip design.
Roseville Shows What It Takes to Build Semiconductor Capacity in Northern California
By Melissa Anguiano, Economic Development Director, City of Roseville, Calif.
Bosch’s up-to-$2 billion conversion of the former TSI Semiconductors fab into a silicon carbide production site shows how federal, state and local partners, an existing site and an experienced workforce can turn a single investment into next-generation manufacturing capacity.
Regards,
Pete Singer, Editor-in-Chief
Semiconductor Digest
www.semiconductordigest.com
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