Welcome to the November/December 2026 Issue of Semiconductor Digest

 

View the November / December Issue


In this issue:

High NA EUV Arrives in Albany: The Ecosystem Behind 2 nm and Beyond
 
As the first high NA EUV scanner is installed at NY Creates’ Albany NanoTech Complex, speakers from NY Creates, IBM, Rapidus and Micron explain why edge placement, stochastics and ecosystem collaboration will decide what comes after 2 nm.
 
The New Bottleneck Stack: How Materials, Substrates, Test and Capacity Now Control AI Supply
By Bilal Hachemi, Ph.D., Senior Technology & Market Analyst, Semiconductor Packaging, Yole Group
 
As AI pushes the advanced packaging market from $55 billion in 2025 to $109 billion in 2031, the real constraint is no longer OSAT capacity alone, but the synchronized availability of materials, substrates, equipment, test infrastructure and qualified process know-how.
 
Characterizing Particle Contamination Sources in Semiconductor Process Tools
By Prasanna Loganathan, Lead Cleanroom Contamination Control Engineer
 
Field data from high-volume 300 mm fabs show where process-tool particles come from, how the dominant sources are shifting, and what engineers can do to shorten post-PM recovery.
 
Connection Integrity in Semiconductor Gas and Fluid Delivery Systems
By Rimas A. Polikaitis, Capital Projects Manager, Veriflo Division, Parker Hannifin
 
Balancing purity, leak tightness and serviceability across UHP face seal fittings, modular surface-mount seals, compression tube fittings and orbital weld joints.
 
Why CMP Needs an Inline Answer to Slurry Agglomeration
By Kalp Kartik Varma, Independent Researcher
 
Slurry doesn’t fail all at once — it fails in a small fraction of oversized particles that today’s inline monitors can’t see and offline particle counters can’t catch in time.
 
Why UV Lasers Are Ideal for Semiconductor Processing
By Alex Laymon, President and Director, DPSS Lasers, a Laserax Company
 
Shorter wavelengths, tighter focus and minimal heat input make UV lasers a versatile tool for wafer marking, scribing, cleaning and depaneling.
 
Faster Fabs Start with Smarter Infrastructure Planning
By Ketan Maroo, Client Segment Director, Semiconductors, Black & Veatch

Modular utility infrastructure can help semiconductor manufacturers bring capacity online faster, align capital spending with demand and preserve flexibility as production requirements evolve.
 
Why Materials Are Driving the Next Era of Semiconductor Innovation
By René Jonker, Executive Vice President and Chief Product Officer, Soitec

The semiconductor roadmap has become a materials roadmap. Supply, cost and integration will decide how quickly engineered substrates can scale.
 
When Does the Next Node Earn the Volume?

By Ron Honig, Managing Partner & Co-CEO, From-Honig Family Office
 
Fourteen years after Nvidia highlighted the pressure rising wafer prices were putting on scaling economics, the decisions around TSMC A14 and Intel 14A show how much more complex the move to a new process generation has become.
 
Positioning India in the Global Semiconductor Value Chain
By Angana Guha Roy, International Affairs Researcher and Strategist
 
As India moves from announcing semiconductor projects to producing commercial chips, the second phase of the India Semiconductor Mission aims to build on the country’s strengths in chip design and 2.5D/3D packaging to make it a critical node in the global supply chain.
 
Meet Today’s Engineering Students Who Are Building Our Future
By Y.C. Wang, Director, Global Academic Programs, DigiKey
 
From rocket launch systems and autonomous rovers to satellites and prosthetic devices, today’s engineering students are using hands-on projects to prepare for their careers — and offering a glimpse of the industry’s future workforce


Regards,

Pete Singer, Editor-in-Chief
Semiconductor Digest
www.semiconductordigest.com

 
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